ST7PLITE30F2B6TR View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7PLITE30F2B6TR

8-bit MCU with single voltage Flash, data EEPROM, ADC, timers, SPI, LINSCI™

STMicroelectronics 

ST7LITE3xF2

I/O PORTS (Cont’d)

Figure 31. I/O Port General Block Diagram

REGISTER

ACCESS

DR

ALTERNATE

OUTPUT

1

From on-chip peripheral

0

ALTERNATE

ENABLE

BIT

VDD

P-BUFFER

(see table below)

PULL-UP

(see table below)

VDD

DDR

OR

OR SEL

If implemented

DDR SEL

DR SEL

1

0

PULL-UP

CONDITION

N-BUFFER

CMOS

SCHMITT

TRIGGER

EXTERNAL

INTERRUPT

Combinational

Logic

REQUEST (eix)

SENSITIVITY

SELECTION

FROM

OTHER

BITS Note: Refer to the Port Configuration

table for device specific information.

PAD

DIODES

(see table below)

ANALOG

INPUT

ALTERNATE

INPUT

To on-chip peripheral

Table 9. I/O Port Mode Options

Input

Output

Configuration Mode

Floating with/without Interrupt

Pull-up with/without Interrupt

Push-pull

Open Drain (logic level)

True Open Drain

Pull-Up

Off

On

Off

NI

P-Buffer

Off

On

Off

NI

Diodes

to VDD

to VSS

On

On

NI (see note 1)

Legend: NI - not implemented

Off - implemented not activated

On - implemented and activated

Note 1: The diode to VDD is not implemented in the

true open drain pads. A local protection between

the pad and VOL is implemented to protect the de-

vice against positive stress.

Note 2: For further details on port configuration,

please refer to Table 11 and Table 12 on page 51.

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