
ST7LITE3xF2
Figure 13. Clock Management Block Diagram
CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 RCCR
CR1 CR0
SICSR
Tunable
1% RC Oscillator
1MHz
OSCRANGE[2:0]
Option bits
CLKIN
CLKIN
fCLKIN CLKIN
/2
DIVIDER
CLKIN/2 (Ext Clock)
RC OSC
8MHz
PLL 1MHz -> 8MHz
PLL 1MHz -> 4MHz 4MHz
PLL
Clock
fOSC
OSC Option bit
PLLx4x8
OSC,PLLOFF,
OSCRANGE[2:0]
Option bits
CLKIN/
OSC1
OSC2
OSC
1-16 MHZ
or 32kHz
/2
DIVIDER
Crystal OSC /2
fOSC /32 DIVIDER
8-BIT
LITE TIMER 2 COUNTER
fOSC/32
1
fOSC 0
fLTIMER
(1ms timebase @ 8 MHz fOSC)
fCPU
TO CPU AND
PERIPHERALS
MCO SMS MCCSR
fCPU
MCO
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