ST7LITE3xF2
13.11 10-BIT ADC CHARACTERISTICS
Subject to general operating condition for VDD, fOSC, and TA unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ 1)
Max
fADC
VAIN
RAIN
ADC clock frequency
Conversion voltage range 2)
External input resistor
0.5
VSSA
4
VDDA
10 3)
CADC Internal sample and hold capacitor
6
tSTAB Stabilization time after ADC enable
0 4)
Conversion time (Sample+Hold)
tADC - Sample capacitor loading time
fCPU=8MHz, fADC=4MHz
3.5
4
- Hold conversion time
10
Unit
MHz
V
kΩ
pF
µs
1/fADC
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
lines and are not tested.
2. When VDDA and VSSA pins are not available on the pinout, the ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than10kΩ). Data
based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first tLOAD. The first conversion after the enable is then
always valid.
Figure 103. Typical Application with ADC
VDD
VAIN
RAIN
AINx
VT
0.6V
VT
0.6V
IL
±1µA
10-Bit A/D
Conversion
CADC
ST72XXX
157/173