STM32F21xxx
Electrical characteristics
Table 19. Typical and maximum current consumption in Sleep mode
Typ
Max(1)
Symbol Parameter
Conditions
fHCLK
TA = 25 °C TA = 85 °C
TA =
105 °C
Unit
120 MHz
38
51
61
90 MHz
30
43
53
60 MHz
20
33
43
30 MHz
11
External clock(2),
all peripherals enabled(3)
25 MHz
8
16 MHz
6
25
35
21
31
19
29
8 MHz
3.6
17.0
27.0
4 MHz
2.4
15.4
25.3
IDD
Supply current in
Sleep mode
2 MHz
1.9
120 MHz
8
14.9
24.7
mA
21
31
90 MHz
7
20
30
60 MHz
5
18
28
External clock(2), all
peripherals disabled
30 MHz
3.5
25 MHz
2.5
16 MHz
2.1
16.0
26.0
16.0
25.0
15.1
25.0
8 MHz
1.7
15.0
25.0
4 MHz
1.5
14.6
24.6
2 MHz
1.4
14.2
24.3
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 4 MHz and PLL is on when fHCLK > 25 MHz.
3. Add an additional power consumption of 1.6 mA per ADC for the analog part. In applications, this consumption occurs only
while the ADC is on (ADON bit is set in the ADC_CR2 register).
Doc ID 17050 Rev 8
73/173