STM32F215IEH6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

STM32F215IEH6

ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/128+4KB RAM, crypto, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

STM32F21xxx

Electrical characteristics

Figure 60. Synchronous non-multiplexed PSRAM write timings

tw(CLK)

tw(CLK)

BUSTURN = 0

FSMC_CLK

td(CLKL-NExL)

FSMC_NEx

Data latency = 0

td(CLKL-NExH)

td(CLKL-NADVL)

FSMC_NADV

td(CLKL-NADVH)

FSMC_A[25:0]

td(CLKL-AV)

td(CLKL-AIV)

FSMC_NWE

td(CLKL-NWEL)

td(CLKL-NWEH)

FSMC_D[15:0]

td(CLKL-Data)

td(CLKL-Data)

D1

D2

FSMC_NWAIT

(WAITCFG = 0b, WAITPOL + 0b)

tsu(NWAITV-CLKH)

FSMC_NBL

td(CLKL-NBLH)

th(CLKH-NWAITV)

Table 76. Synchronous non-multiplexed PSRAM write timings(1)(2)

Symbol

Parameter

Min

tw(CLK) FSMC_CLK period

td(CLKL-NExL) FSMC_CLK low to FSMC_NEx low (x=0..2)

td(CLKL-NExH) FSMC_CLK low to FSMC_NEx high (x= 0…2)

td(CLKL-NADVL) FSMC_CLK low to FSMC_NADV low

td(CLKL-

NADVH)

FSMC_CLK low to FSMC_NADV high

td(CLKL-AV) FSMC_CLK low to FSMC_Ax valid (x=16…25)

td(CLKL-AIV) FSMC_CLK low to FSMC_Ax invalid (x=16…25)

td(CLKL-NWEL) FSMC_CLK low to FSMC_NWE low

td(CLKL-NWEH) FSMC_CLK low to FSMC_NWE high

td(CLKL-Data) FSMC_D[15:0] valid data after FSMC_CLK low

td(CLKL-NBLH) FSMC_CLK low to FSMC_NBL high

1. CL = 30 pF.

2. Based on characterization, not tested in production.

2THCLK- 1

-

1

-

6

-

8

-

1

-

2

ai14993g

Max Unit

-

ns

1

ns

-

ns

5

ns

-

ns

0

ns

-

ns

1

ns

-

ns

2

ns

-

ns

Doc ID 17050 Rev 8

131/173

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