PC48F2000P0VB00 View Datasheet(PDF) - Intel

Part Name

Description

MFG CO.

PC48F2000P0VB00

Intel StrataFlash® Embedded Memory

Intel 

1-Gbit P30 Family

12.0

12.1

12.2

Erase Operations

Flash erasing is performed on a block basis. An entire block is erased each time an erase command

sequence is issued, and only one block is erased at a time. When a block is erased, all bits within

that block read as logical ones. The following sections describe block erase operations in detail.

Block Erase

Block erase operations are initiated by writing the Block Erase Setup command to the address of

the block to be erased (see Section 9.2, “Device Commands” on page 50). Next, the Block Erase

Confirm command is written to the address of the block to be erased. If the device is placed in

standby (CE# deasserted) during an erase operation, the device completes the erase operation

before entering standby.VPP must be above VPPLK and the block must be unlocked (see Figure 44,

“Block Erase Flowchart” on page 89).

During a block erase, the Write State Machine (WSM) executes a sequence of internally-timed

events that conditions, erases, and verifies all bits within the block. Erasing the flash memory array

changes “zeros” to “ones”. Memory array bits that are ones can be changed to zeros only by

programming the block (see Section 11.0, “Programming Operations” on page 61).

The Status Register can be examined for block erase progress and errors by reading any address.

The device remains in the Read Status Register state until another command is written. SR[0]

indicates whether the addressed block is erasing. Status Register bit SR[7] is set upon erase

completion.

Status Register bit SR[7] indicates block erase status while the sequence executes. When the erase

operation has finished, Status Register bit SR[5] indicates an erase failure if set. SR[3] set would

indicate that the WSM could not perform the erase operation because VPP was outside of its

acceptable limits. SR[1] set indicates that the erase operation attempted to erase a locked block,

causing the operation to abort.

Before issuing a new command, the Status Register contents should be examined and then cleared

using the Clear Status Register command. Any valid command can follow once the block erase

operation has completed.

Erase Suspend

Issuing the Erase Suspend command while erasing suspends the block erase operation. This allows

data to be accessed from memory locations other than the one being erased. The Erase Suspend

command can be issued to any device address. A block erase operation can be suspended to

perform a word or buffer program operation, or a read operation within any block except the block

that is erase suspended (see Figure 41, “Program Suspend/Resume Flowchart” on page 86).

When a block erase operation is executing, issuing the Erase Suspend command requests the WSM

to suspend the erase algorithm at predetermined points. The device continues to output Status

Register data after the Erase Suspend command is issued. Block erase is suspended when Status

Register bits SR[7,6] are set. Suspend latency is specified in Section 7.5, “Program and Erase

Characteristics” on page 45.

Datasheet

Intel StrataFlash® Embedded Memory (P30)

Order Number: 306666, Revision: 001

April 2005

67

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