PC48F2000P0ZBQ0 View Datasheet(PDF) - Intel

Part Name

Description

MFG CO.

PC48F2000P0ZBQ0

Intel StrataFlash® Embedded Memory

Intel 

1-Gbit P30 Family

Figure 27. Reset Operation Waveforms

(A) Reset during

read mode

VIH

RST# [P]

VIL

(B) Reset during

program or block erase

P1 ≤ P2

(C) Reset during

program or block erase

P1 ≥ P2

VIH

RST# [P]

VIL

VIH

RST# [P]

VIL

(D) VCC Power-up to

RST# high

VCC

VCC

0V

P1

R5

Abort

P2

Complete

R5

Abort

P2 Complete

R5

P3

8.3

Power Supply Decoupling

Flash memory devices require careful power supply de-coupling. Three basic power supply current

considerations are: 1) standby current levels; 2) active current levels; and 3) transient peaks

produced when CE# and OE# are asserted and deasserted.

When the device is accessed, many internal conditions change. Circuits within the device enable

charge-pumps, and internal logic states change at high speed. All of these internal activities

produce transient signals. Transient current magnitudes depend on the device outputs’ capacitive

and inductive loading. Two-line control and correct de-coupling capacitor selection suppress

transient voltage peaks.

Because Intel® Multi-Level Cell (MLC) flash memory devices draw their power from VCC, VPP,

and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to ground. High-

frequency, inherently low-inductance capacitors should be placed as close as possible to package

leads.

Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor should be

placed between power and ground close to the devices. The bulk capacitor is meant to overcome

voltage droop caused by PCB trace inductance.

Datasheet

Intel StrataFlash® Embedded Memory (P30)

Order Number: 306666, Revision: 001

April 2005

47

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