
NAND04GA3C2A, NAND04GW3C2A
Table 11. Electronic Signature Byte 3
I/O
Definition
I/O1-I/O0
Internal Chip number
I/O3-I/O2
Cell Type
I/O5-I/O4
Number of simultaneously
programmed pages
I/O7-I/O6
Reserved
Table 12. Electronic Signature Byte 4
I/O
Definition
I/O1-I/O0
Page size
(Without Spare Area)
Spare area size
I/O2
(Byte / 512 Byte)
I/O7, I/O3
Minimum sequential
access time
I/O5-I/O4
I/O6
Block size
(without Spare Area)
Organization
Value
00
01
10
11
00
01
10
11
00
01
10
11
10
Value
00
01
10
11
0
1
00
10
01
11
00
01
10
11
0
1
6 Device operations
Description
1
2
4
8
2-level cell
4-level cell
8-level cell
16-level cell
1
2
4
8
Description
1 KBytes
2 KBytes
Reserved
Reserved
8
16
50ns
30ns
Reserved
Reserved
64 KBytes
128 KBytes
256 KBytes
Reserved
x8
x16
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