PSD8535-12UI View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

PSD8535-12UI

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

STMicroelectronics 

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Decode PLD (DPLD)

The DPLD, shown in Figure 14, is used for decod-

ing the address for internal and external compo-

nents. The DPLD can be used to generate the

following decode signals:

■ 8 Sector Select (FS0-FS7) signals for the

primary Flash memory (three product terms

each)

■ 4 Sector Select (CSBOOT0-CSBOOT3)

signals for the secondary Flash memory (three

product terms each)

Figure 14. DPLD Logic Array

■ 1 internal SRAM Select (RS0) signal (two

product terms)

■ 1 internal CSIOP Select (PSD Configuration

Register) signal

■ 1 JTAG Select signal (enables JTAG on Port

C)

■ 2 internal Peripheral Select signals

(Peripheral I/O mode).

I /O PORTS (PORT A,B,C)

(INPUTS)

(24)

MCELLAB.FB [7:0] (FEEDBACKS)

(8)

MCELLBC.FB [7:0] (FEEDBACKS)

(8)

PGR0 - PGR7

(8)

A[15:0] *

(16)

PD[2:0] (ALE,CLKIN,CSI)

(3)

PDN (APD OUTPUT)

(1)

CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (3)

RESET

(1)

RD_BSY

(1)

3

CSBOOT 0

3

CSBOOT 1

3

CSBOOT 2

3

CSBOOT 3

3

FS0

3

FS1

3

FS2

3

FS3

8 PRIMARY FLASH

3

MEMORY SECTOR SELECTS

FS4

3

FS5

3

FS6

3

FS7

2

RS0

SRAM SELECT

1

CSIOP

I/O DECODER

SELECT

1

PSEL0

PERIPHERAL I/O MODE

1

PSEL1

SELECT

1

JTAGSEL

AI02873D

35/110

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