PSD813F2A-15M View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD813F2A-15M Datasheet PDF : 128 Pages
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I/O ports
PSD8XXFX
Table 20. Port operating modes (continued)
Port mode
Port A
Port B
Address Out
Address In
Yes (A7 – 0)
Yes
Yes (A7 – 0)
or (A15 – 8)
Yes
Data port
Peripheral I/O
JTAG ISP
Yes (D7 – 0)
No
Yes
No
No
No
1. Can be multiplexed with other I/O functions.
Port C
No
Yes
No
No
Yes(1)
Port D
No
Yes
No
No
No
Table 21. Port operating mode settings
Mode
Defined in
PSDabel
Defined in PSD
configuration
Control Direction
register register
setting setting
VM
register
setting
JTAG Enable
MCU I/O
PLD I/O
Data port (Port A)
Address Out
(Port A,B)
Address In
(Port A,B,C,D)
Peripheral I/O
(Port A)
JTAG ISP(3)
Declare pins only
N/A(1)
Logic equations
N/A
N/A
Specify bus type
Declare pins only
N/A
Logic for equation
input macrocells
Logic equations
(PSEL0 & 1)
JTAGSEL
N/A
N/A
JTAG
Configuration
1 = output,
0
0 = input(2)
N/A
N/A
N/A
(2)
N/A
N/A
N/A
N/A
N/A
N/A
1
1(2)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A PIO bit = 1
N/A
N/A
N/A
N/A JTAG_Enable
1. N/A = Not Applicable
2. The direction of the port A,B,C, and D pins are controlled by the Direction register ORed with the individual output enable
product term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on port C.
Table 22. I/O port Latched address output assignments
MCU
Port A (PA3-PA0) Port A (PA7-PA4)
8051XA (8-Bit)
N/A(1)
Address a7-a4
80C251
N/A
N/A
(Page mode)
All Other
8-Bit Multiplexed
Address a3-a0
Address a7-a4
8-Bit
N/A
N/A
Non-Multiplexed bus
1. N/A = Not Applicable
Port B (PB3-PB0)
Address a11-a8
Address a11-a8
Address a3-a0
Address a3-a0
Port B (PB7-PB4)
N/A
Address a15-a12
Address a7-a4
Address a7-a4
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Doc ID 7833 Rev 7
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