PSD834F5A-70UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD834F5A-70UI Datasheet PDF : 128 Pages
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PSD8XXFX
PSD register description and address offset
Table 8. Register address offset (continued)
Register
name
Port A
Port B
Port C
Port D
Other
(1)
Description
Mask
macrocells 22 22
AB
Blocks writing to the Output macrocells
AB
Mask
macrocells
BC
Primary Flash
Protection
Secondary
Flash memory
Protection
JTAG Enable
PMMR0
23 23
Blocks writing to the Output macrocells
BC
C0
Read only – Primary Flash Sector
Protection
C2
Read only – PSD Security and Secondary
Flash memory Sector Protection
C7 Enables JTAG port
B0 Power Management register 0
PMMR2
Page
VM
B4 Power Management register 2
E0 Page register
E2
Places PSD memory areas in program
and/or data space on an individual basis.
1. Other registers that are not part of the I/O ports.
Doc ID 7833 Rev 7
25/128
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