
PSD8XXFX
AC/DC parameters
Figure 41. Asynchronous Reset / Preset
tARPW
RESET/PRESET
INPUT
REGISTER
OUTPUT
tARP
AI02864
Figure 42. Asynchronous Clock mode Timing (product term clock)
tCHA
tCLA
CLOCK
INPUT
REGISTERED
OUTPUT
tSA tHA
tCOA
AI02859
Table 52. CPLD macrocell asynchronous clock mode timing (5 V devices)
Symbol Parameter
Conditions
-70
-90
Min Max Min Max
-15
Min Max
PT Turbo Slew
Aloc off rate
Unit
fMAXA
tSA
tHA
tCHA
tCLA
Maximum
frequency
External
feedback
1/(tSA+tCOA)
Maximum
frequency
Internal
feedback
1/(tSA+tCOA–10)
(fCNTA)
Maximum
frequency
Pipelined data
1/(tCHA+tCLA)
Input setup
time
7
Input hold
time
8
Clock input
high time
9
Clock input
low time
9
38.4
26.32
21.27
62.5
35.71
27.78
71.4
41.67
35.71
8
12
+2
12
14
12
15
12
15
+ 10
+ 10
+ 10
MHz
MHz
MHz
ns
ns
ns
ns
Doc ID 7833 Rev 7
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