CS89712 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS89712 Datasheet PDF : 170 Pages
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CS89712
FIFO operation complete bit (FIFO) is set in the DAI status register before writing another value to this
register.
Bit
0-14
15
16-20
21-31
Reserved
FIFOEN: FIFO Transmit Bit
0 — Disable Transmit
1 — Enable Transmit
FIFO CHANNEL SELECT:
01101b — Left channel select
10001b — Right channel select
Reserved
Description
Table 61. DAI Data Register 2
3.16.6 DAISR DAI Status (address 0x8000.2100)
The DAI Status register (DAISR) contains bits which signal FIFO overrun and underrun errors and
FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller.
The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not empty,
when a FIFO operation is complete, and when the right channel or left channel portion of the CODEC
is enabled (no interrupt generated).
Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is
cleared, the interrupt is cleared. Read / write bits are called status bits, read-only bits are called flags.
Status bits are referred to as “sticky” (once set by hardware, they must be cleared by software). Writ-
ing a one to a sticky status bit clears it, while writing a zero has no effect. Read-only flags are set and
cleared by hardware, and writes have no effect. Additionally, some bits which cause interrupts have
corresponding mask bits in the control register and are indicated in the section headings below. Note
that the user has the ability to mask all DAI interrupts by clearing the DAI bit within the interrupt con-
troller mask register INTMR3.
31-13
Reserved
6
RCNFLCTU
12
FIFO
5
LCRORCRO
11
LCNE
4
LCTURCTU
10
LCNF
3
LCRS
9
RCNE
2
LCTS
8
RCNF
1
LCRSRCRS
7
RCCELCRO
0
LCTSRCTS
Bit
Description
0
RCTS: Right Channel Transmit FIFO Service Request Flag (read-only)
0 — Right Channel Transmit FIFO is more than half full (five or more entries filled) or DAI dis-
abled
1 — Right Channel Transmit FIFO is half full or less (four or fewer entries filled) and DAI oper-
ation is enabled, interrupt request signaled if not masked
(if RCTM = 1)
Table 62. DAI Control, Data and Status Register Locations
DS502PP2
111
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