LTC2205-14
APPLICATIONS INFORMATION
PGA Pin
The PGA pin selects between two gain settings for the ADC
front-end. PGA = 0 selects an input range of 2.25VP-P;
PGA = 1 selects an input range of 1.5VP-P. The 2.25V input
range has the best SNR; however, the distortion will be
higher for input frequencies above 100MHz. For applica-
tions with high input frequencies, the low input range will
have improved distortion; however, the SNR will be worse
by up to approximately 2dB. See the Typical Performance
Characteristics section.
Driving the Encode Inputs
The noise performance of the LTC2205-14 can depend on
the encode signal quality as much as on the analog input.
The encode inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a
1.6V bias. The bias resistors set the DC operating point
for transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
Any noise present on the encode signal will result in ad-
ditional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequen-
cies), take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude possible. If using trans-
former coupling, use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a fixed frequency sinusoidal
signal, filter the encode signal to reduce wideband
noise.
4. Balance the capacitance and series resistance at both
encode inputs such that any coupled noise will appear
at both inputs as common mode noise.
The encode inputs have a common mode range of 1.2V
to 3V. Each input may be driven from ground to VDD for
single-ended drive.
0.1µF
ENCODE
ETC1-1T
INPUT
••
50Ω
100Ω
50Ω
0.1µF
LTC2205-14 VDD
TO INTERNAL
ADC CLOCK
DRIVERS
ENC+
VDD 1.6V
6k
33pF
ENC–
VDD 1.6V
6k
220514 F08
Figure 8. Transformer Driven Encode
220514fa
19