MITSUBISHI SEMICONDUCTOR < STANDERD LINEAR IC >
M62281P/FP
GENERAL PURPOSE CURRENT MODE PWM CONTROL IC
In Fig. 3-1, AC gain is represented as:
| Av | = | RF/ RIN |
Proper gain setting is about 40dB.
RF should be 52KΩ or more due to the current source capability of error amp.
R1, R2 should meet the condition as below so that the voltage of EAIN terminal should not be over 5V.
R2 * Vcc/ (R1 + R2) ≤ 5V
Due to the input impedance of EAIN terminal, the current in R1, R2 should be less than several mA.
(2) CT(OVP) TERMINAL
Timer type latch circuit works as follows.
Constant charge current flows out from CT terminal to the external capacitor when CLM is operative.
When the voltage of CT terminal rises up to over 4.0V(typ.), the latch circuit operates to make
functions of this IC inoperative. Inoperative status is sustained until supply voltage becomes less than
stop voltage. The value for start-up register has to be set so that the current over 1.8mA(typ.) can flow
the resistor because the stop status has to be kept by the current in start-up resistor R1 shown in
application circuit.
When timer latch circuit is operative, supply current increases at high voltage as shown in Fig.4 to
avoid the damage caused by unnecessarily increased supply voltage.
Inoperative status goes back to operation by forcibly decreasing the voltage of CT terminal to less
than 0.7V.
3.0
2.5
Latch reset
8.3V
2.0
1.5
1.0
0.5
0
5 10 15 20 25 30 35
Supply voltage : Vcc (V)
Fig.4 Supply current/voltage chracteristics (at timer latch)
(5/9)