CS7654 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS7654

CCD Color-Space Processor with Analog Output

Cirrus Logic 

CS7654

ANALOG

Analog Timing

All CS7654 analog timing and sequencing is derived

from 27 MHz clock input. The analog outputs are

controlled internally by the video timing generator in

conjunction with master and slave timing. The video

output signals perform accordingly for NTSC and

PAL specifications.

Being that the CS7654 is almost entirely a digital

circuit, great care has been taken to guarantee ana-

log timing and slew rate performance as specified

in the NTSC and PAL analog specifications. Refer-

ence the Analog Parameters section of this data

sheet for exact performance parameters.

VREF

The CS7654 can operate with or without the aid of

an external voltage reference. The CS7654 is de-

signed with an internal voltage reference generator

that provides a vrefout signal at the VREF pin. The

internal voltage reference is utilized by not making

a connection to the VREF pin. The VREF pin can

also be connected to an external precision

1.232 volt reference, which then overrides the in-

ternal reference.

ISET-DAC

All three of the CS7654 digital to analog converter

DACs are output current normalized with a com-

mon ISET-DAC device pin. The DAC output cur-

rent per bit is determined by the size of the resistor

connected between ISET-DAC pin and electrical

ground. Typically a 4 KΩ, 1% metal film resistor

should be used. The ISET resistance can be

changed by the user to accommodate varying video

output attenuation via post filters and also to suit

individual preferred performance.

In conjunction with the ISET-DAC value, the user

can also independently vary the chroma, luma and

colorburst amplitude levels via host addressable

control register bits that are used to control internal

digital amplifiers. The DAC output levels are de-

fined by the following operations:

VREF/RISET = IREF

(e.g., 1.232 V/4K Ω = 308 µA)

COMP_VID/Y/C outputs in low impedance mode:

VOUT (max) = IREF*112.88*37.5 Ω = 1.304V

COMP_VID/Y/C outputs in high impedance mode:

VOUT (max) = IREF*28.22*150Ω = 1.304 V

DACs

The CS7654 is equipped with three independent,

video-grade, current-output, digital-to-analog con-

verters (DACs). They are 10-bit DACs operating at

a 27 MHz two-times-oversampling rate. All three

DACs are disabled and default to a low power

mode upon RESET. Each DAC can be individually

powered down and disabled. The output-current-

per-bit of all three DACs is determined by the size

of the resistor connected between the ISET_DAC

pin and electrical ground.

Luminance DAC

The SVID_Y pin is driven from a 10-bit 27 MHz

current output DAC that internally receives the

SVID_Y, or luminance portion, of the video signal

(black and white only). SVID_Y is designed to

drive proper video levels into a 37.5 Ω load. Refer-

ence the detailed electrical section of this data sheet

for the exact SVID_Y digital to analog AC and DC

performance data. A EN_L enable control bit in the

Control Register 5 (0×05 at SA 0x00h) is provided

to enable or disable the luminance DAC. For a

complete disable and lower power operation the lu-

minance DAC can be totally shut down via the

SVIDLUM_PD control bit in the Control Register 4

(0×04 at SA 0x00h). In this mode, turn-on through

the control register will not be instantaneous.

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