CS61884 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS61884

Octal T1/E1/J1 Line Interface Unit

Cirrus Logic 

CS61884

19.7 Master Clock Switching Characteristics

Parameter

MASTER CLOCK (MCLK)

Master Clock Frequency

Master Clock Frequency

Master Clock Tolerance

Master Clock Duty Cycle

Symbol Min.

E1 Modes

T1/J1 Modes

MCLK

MCLK

-

-

-100

40

19.8 Transmit Switching Characteristics

Parameter

E1 TCLK Frequency

E1 TPOS/TNEG Pulse Width (RZ Mode)

T1/J1 TCLK Frequency

TCLK Tolerance (NRZ Mode)

TCLK Duty Cycle

TCLK Pulse Width

TCLK Burst Rate

Note 22

TPOS/TNEG to TCLK Falling Setup Time (NRZ Mode)

TCLK Falling to TPOS/TNEG Hold time (NRZ Mode)

TXOE Asserted Low to TX Driver HIGH-Z

TCLK Held Low to Driver HIGH-Z

Note 21

Symbol

1/tpw2

1/tpw2

tpwh2/tpw2

tsu2

th2

Min.

-

236

-

-50

-

20

-

25

25

-

8

19.9 Receive Switching Characteristics

* All parameters guaranteed by production, characterization or design.

Parameter

RCLK Duty Cycle

E1 RCLK Pulse Width

E1 RPOS/RNEG Pulse Width (RZ Mode

E1 RPOS/RNEG to RCLK rising setup time

E1 RPOS/RNEG to RCLK hold time

T1/J1 RCLK Pulse Width

T1/J1 RPOS/RNEG Pulse Width (RZ Mode)

T1/J1 POS/RNEG to RCLK rising setup time

T1/J1 RPOS/RNEG to RCLK hold time

RPOS/RNEG Output to RCLK Output (RZ Mode)

Rise/Fall Time, RPOS, RNEG, RCLK, LOS outputs

Symbol

tsu

th

tsu

th

tr, tf

Min.

40

196

200

150

200

259

250

150

200

-

-

Notes: 20. Output load capacitance = 50pF.

21. MCLK is not active.

22. Parameters guaranteed by design and characterization.

Typ Max

2.048

1.544

50

+100

60

Typ Max

2.048

-

244 252

1.544

-

-

50

-

90

-

-

-

20

-

-

-

-

-

1

12

20

Typ Max

50

60

244 328

244 300

244

-

244

-

324 388

324 400

324

-

324

-

-

10

-

85

Units

MHz

MHz

ppm

%

Units

MHz

nS

MHz

PPM

%

nS

MHz

nS

nS

µS

µS

Units

%

nS

nS

nS

nS

nS

nS

nS

nS

nS

nS

DS485F1

59

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