CS5317-KP View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5317-KP Datasheet PDF : 32 Pages
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CDB5317
the board and then connected to the VA+ and VA-
supply pins of the chip. The +5 V and -5V are
then connected by means of ten Ω resistors to the
VD+ and VD- pins respectively. Capacitive filter-
ing is provided on all supply pins of the chip. In
addition there is a 0.1 µF filter capacitor con-
nected from the REFBUF pin of the chip to the
VA- supply pin.
To properly operate, the CS5317 chip requires an
external (5 V CMOS compatible) clock. A BNC
connector labeled CLKIN is provided to connect
the off-board clock signal to the board. The
CLKIN signal is also available on the 40 pin
header connector. The CLKIN signal is one input
to the phase detector of the on-chip phase locked
loop of the CS5317.
Header connector P2 (see Figure 2) is provided to
allow mode selection for the CS5317 chip. The
mode selection works together with the CLKIN
signal to set the sample rate and the output word
rate of the CS5317. See the CS5317 data sheet
for details on mode selection. Two of the avail-
able modes (CLKG1 and CLKG2) utilize the
on-chip phase locked loop to step up the CLKIN
frequency to obtain the necessary sample rate
clock for the A/D converter. Another mode (the
CLKOR mode) does not use the on-chip PLL but
instead drives the sample function directly. The
U5
1
2
3
4
9
8
11
10
13
12
DOUT
(fig. 2)
VL
14
1
2
7
C1
0.1 µF
13
12
UNUSED GATES
CLKOUT 3
4
(fig. 2)
U1
5
6
VL
10
VL
12
D
S
Q9
VL 11 U4
DATA
11
10 9
8
CL
(fig. 2)
8
RQ
VL
13
DOUT2
VL
(fig. 6)
14 4
S
2
D U4 Q
3 74HC74
CL
Q
GND R
C10
0.1 µF
D TP2
5
6
VL
DRDY
(fig. 6)
7
0.1 µF
VL TP3
C11 14
6
5
U5
7
R4
DACK
(fig. 6)
10k
CLKOUT
(fig. 6)
CLKOUT2
(fig. 6)
DATA 1
(fig. 6)
DATA
(fig. 6)
Figure 3. Buffers and Parallel Handshake Flip-Flop
28
DS27DB3
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