CS5102A-KL View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5102A-KL Datasheet PDF : 40 Pages
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CS5101A CS5102A
+5VA
+
10
+
4.7 µF 0.1 µF
0.1 µF 1 µF
VD+
Mode Control
Voltage Reference
Analog
Sources
50
*
1 nF
50
*
1 nF
* For best dynamic
S/(N+D) performance.
25
VA+
26
7
TST VD+
XOUT 4
18 OUTMOD
27 SCKMOD
17 BP/UP
16
CODE
CS5101A
OR
20
VREF
CS5102A
22 AGND
XTAL
CLKIN 3
10 M
2
RST
28
SLEEP
5
STBY
CH1/2 13
CRS/FIN 10
HOLD 12
Control
Logic
19 AIN1
NPO
8
TRK1
9
TRK2
11
SSH/SDL
24
AIN2
NPO
21
REFBUF
SCLK 14
SDATA 15
DGND 6
Data
Interface
C1
C2 = C1
EXT
CLOCK
XTAL & C1 Table
XTAL C1, C2
CS5101A
8.0 MHz
FRN
10 pF
PDT, RBT, 8.192 MHz 10 pF
SSC
CS5102A
1.6 MHz
FRN
30 pF
PDT, RBT,
1.6 MHz
or
SSC
2.0 MHz
30 pF
-5VA
0.1 µF
VA-
VD-
23
1
10
Unused Logic inputs should
be tied to VD+ or DGND.
+ 4.7 µF
0.1 µF
0.1 µF + 1 µF
Figure 7. CS5101A/CS5102A System Connection Diagram
calibration cycle on the CS5102A takes
2,882,040 master clock cycles to complete (ap-
proximately 1.8 seconds with a 1.6 MHz master
clock). The CS5101A’s and CS5102A’s STBY
be less than or equal to 10 kΩ. The system power
supplies, voltage reference, and clock should all
be established prior RST rising.
output remains low throughout the calibration se- Single-Channel Operation
quence, and a rising transition indicates the
device is ready for normal operation. While cali-
brating, the CS5101A and CS5102A will ignore
changes on the HOLD input.
The CS5101A and CS5102A can alternatively be
used to sample one channel by tying the CH1/2
input high or low. The unused AIN pin should be
To perform the reset function, a simple power-on
reset circuit can be built using a resistor and ca-
tied to the analog input signal or to AGND. (If
operating in free run mode, AIN1 and AIN2 must
pacitor as shown in Figure 8. The resistor should
DS45F2
19
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