Z8038018FSC View Datasheet(PDF) - Zilog

Part Name

Description

MFG CO.

Z8038018FSC

MICROPROCESSOR

Zilog 

ZILOG

Standby Mode Exit With Bus Request

Optionally, if the BRXT bit of the Standby Mode Control

Register (SMCR) was previously set, /STNBY goes to logic

1 when the /BREQ input is asserted, allowing the external

crystal oscillator that drives the Z380 MPU’s CLK input to

restart. A warm-up counter internal to the Z380 MPU

proceeds to count, for a duration long enough for the

oscillator to stabilize, which was selected with the WM bits

in the SMCR. When the counter reaches its end-count,

clocking resumes within the Z380 MPU and at the BUSCLK

and IOCLK outputs.

BUSCLK

MICROPROCESSOR

The Z380 MPU relinquishes the system bus after clocking

resumes, with the normal /BREQ, /BACK handshake pro-

cedure. The Z380 MPU regains the system bus when

/BREQ goes inactive, again going through a normal hand-

shake procedure.

Note that clocking continues, and the Z380 MPU is at the

halt state.

Bus Release

Halt

State

IOCLK

/STNBY

/BREQ

/BACK

ADDRESS

FFFFFFFFH

DATA

BUS

CNTLS

Figure 52. Standby Mode Exit with Bus Request Timing

PS010001-0301

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