Z8038018FSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
Z8038018FSC Datasheet PDF : 115 Pages
| |||
ZILOG
MICROPROCESSOR
Mnemonic
LDCTL SR,HL
LDCTL A,v
LDCTL v,A
LDCTL v,n
SETC LCK
SETC LW
SETC XM
RESC LCK
RESC LW
BTEST
MTEST
Symbolic
Operation
Flags
P/
SZ x Hx VNC
SR(15-8) ← HL(15-8)
SR(0) ← HL(0)
••x•x•••
if (LW)
SR(31-16) ← HL(31-16)
else
SR(31-24) ← HL(15-8)
SR(23-16) ← HL(15-8)
v←A
••x•x•••
A←v
••x•x•••
v←n
••x•x•••
SR(1) ← 1
Set Lock mode
SR(6) ← 1
Set Long word mode
SR(7) ← 1
Set Extend mode
SR(1) ← 0
Reset Lock mode
SR(6) ← 0
Reset Long word mode
Bank Test
S ← SR(16)
Z ← SR(24)
V ← SR(0)
C ← SR(8)
Mode test
S ← SR(7)
Z ← SR(6)
C ← SR(1)
••x•x•••
••x•x•••
••x•x•••
••x•x•••
••x•x•••
¤¤x•x¤•¤
¤¤x•x••¤
Opcode
# of Execute
76 543 210 HEX Bytes Time Notes
11 101 101 ED 2
4
L1
11 001 000 C8
11 vv1 101
2
2
11 010 000 D0
11 vv1 101
2
4
11 011 000 D8
11 vv1 101
3
4
11 011 010 DA
← n →
11 101 101 ED 2
4
11 110 111 F7
11 011 101 DD 2
4
11 110 111 F7
11 111 101 FD 2
4
11 110 111 F7
11 101 101 ED 2
4
11 111 111 FF
11 011 101 DD 2
4
11 111 111 FF
11 101 01 ED 2
2
11 001 111 CF
11 011 101 DD 2
2
11 001 111 CF
vv
Control Regs
01
XSR
10
DSR
11
YSR
Notes:
Instructions in Italic face are Z380 new instructions, instructions with underline are Z180 original instructions.
L1: In Long Word mode, this instruction loads in 32 bits; dst(31-0) ← src(31-0)
L9: In Long Word mode, this instruction operates in 32-bits; If A(7) = 0 then HL(31-16) = 0000h else FFFFh
@: Converts accumulator content into packed BCD following add or subtract with packed BCD operands.
#: Interrupts are not sampled at the end of EI and DI.
PS010001-0301
Share Link: 