CS8401A-CS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8401A-CS Datasheet PDF : 34 Pages
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CS8401A CS8402A
(619) 268-2400
All internal timing is derived from MCK. On the
Part Number: PE65612
CS8402A, MCK is always 128×Fs. On the
CS8401A, the external MCK is programmable
Schott Corporation
1000 Parkers Lane Rd.
Wayzata, MN 55391
(612) 475-1173
FAX (612) 475-1786
and is initially divided to 128×Fs before being
used by the part. The internal clock IMCK used
in the following discussion is always 128×Fs re-
gardless of the external MCK pin.
Part Number:
67125450 - compatible with Pulse
67128990 - lower cost
67129000 - surface mount
67129600 - single shield
After RST, the CS8401A and CS8402A syn-
chronize the internal timing to the audio data
port, more specifically FSYNC, to guarantee that
channel A is left channel data and channel B is
right channel data as per the AES/EBU specifica-
Scientific Conversions Inc.
42 Truman Drive
Novato, CA. 94947
tion. If FSYNC moves with respect to IMCK,
the transmitter could lose synchronization, which
causes an internal reset.
(415) 8922323
Part Number:
SC916-01 - single shield
SC916-02 - surface mount
Figure B1 shows the structure of the serial port
input, to the transmitter output. The audio data is
serially shifted into R1. PLD is an internal signal
that parallel loads R1 into the R2 buffer, and, at
the same time, the C, U, and V bits are latched.
Appendix B: MCK and FSYNC Relationship
On the CS8401A, the C, U, and V bits are held
in RAM, whereas on the CS8402A, they are
FSYNC should be derived either directly or indi-
rectly from MCK. The indirect case could be a
DSP, providing FSYNC through its serial port,
using the same master oscillator that generates
MCK. In either case, FSYNC’s relationship to
MCK is fixed and does not move. Since this ap-
pendix provides information on what would
happen if FSYNC did move with respect to
MCK, it does not apply to the majority of users.
latched from external pins. The PLD signal rises
on the first SCK edge that can latch data. This is
coincident with the latching of the MSB of audio
data in MSB-first, left-justified modes. PLD
stays high for one SCK period. In the CS8402A
section, the arrows on SCK in Figure 16 indicate
when PLD goes high. Also, SBC in the
CS8402A CD submode is an external version of
PLD gated by the SBF input.
SDATA
SCK
R1 - Shift (in) Register
internally generated
PLD (load signal)
+V
PCUV
R2 - Audio Buffer
D Q Internal Reset
CS8402A C,U,V Port
CS8401A Internal
Memory
LDS (load signal)
IMCK
2
R3 - Shift (out) Register
Preamble
Mux Biphase
Encode
TXP
Dri-
ver
TXN
Figure B1. Serial Port-to-Transmitter Block Diagram
DS60F1
29
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