CMOS Sensor; Customer Datasheet, Rev 3.0, 28 September 2000
VV5410 & VV6410
9.7 Serial Interface Timing
Parameter
Symbol
Min.
Max.
SCL clock frequency
fscl
0
100
Bus free time between a stop and a start
tbuf
2
-
Hold time for a repeated start
thd;sta
80
-
LOW period of SCL
tlow
320
-
HIGH period of SCL
thigh
160
-
Set-up time for a repeated start
tsu;sta
80
-
Data hold time
thd;dat
0
-
Data Set-up time
tsu;dat
0
-
Rise time of SCL, SDA
tr
-
300
Fall time of SCL, SDA
tf
-
300
Set-up time for a stop
tsu;sto
80
-
Capacitive load of each bus line (SCL,
Cb
SDA)
-
200
Table 58 : Serial Interface Timing Characteristics
Unit
kHz
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
stop start
SDA
start
stop
...
SCL
tbuf
tlow tr
tf
...
thd;sta
thd;sta
thd;dat
thigh tsu;dat
tsu;sta
tsu;sto
Figure 45 : Serial Interface Timing Characteristics
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