ST7FMC2N6B6(2004) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7FMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

16-BIT TIMER (Cont’d)

3. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-

nected to the timer. The ICAP2 pin can be used

to perform input capture (ICF2 can be set and

IC2R can be loaded) but the user must take

care that the counter is reset each period and

9.3.4 Low Power Modes

ICF1 can also generates interrupt if ICIE is set.

4. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the

PWM mode is the only active one.

Mode

WAIT

HALT

Description

No effect on 16-bit Timer.

Timer interrupts cause the Device to exit from WAIT mode.

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous

count when the Device is woken up by an interrupt with “exit from HALT mode” capability or from the counter

reset value when the Device is woken up by a RESET.

If an input capture event occurs on the ICAPi pin, the input capture detection circuitry is armed. Consequent-

ly, when the Device is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and

the counter value present when exiting from HALT mode is captured into the ICiR register.

9.3.5 Interrupts

Interrupt Event

Input Capture 1 event/Counter reset in PWM mode

Input Capture 2 event

Output Compare 1 event (not available in PWM mode)

Output Compare 2 event (not available in PWM mode)

Timer Overflow event

Event

Flag

ICF1

ICF2

OCF1

OCF2

TOF

Enable

Control

Bit

ICIE

OCIE

TOIE

Exit

from

Wait

Yes

Yes

Yes

Yes

Yes

Exit

from

Halt

No

No

No

No

No

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-

ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt

mask in the CC register is reset (RIM instruction).

9.3.6 Summary of Timer modes

MODES

Input Capture (1 and/or 2)

Output Compare (1 and/or 2)

One Pulse Mode

PWM Mode

Input Capture 1

Yes

Yes

No

No

AVAILABLE RESOURCES

Input Capture 2 Output Compare 1 Output Compare 2

Yes

Yes

Yes

Yes

Yes

Not Recommended1)

No

Not Recommended3)

No

Yes

Partially 2)

No

1) See note 4 in Section 9.3.3.5 One Pulse Mode

2) See note 5 in Section 9.3.3.5 One Pulse Mode

3) See note 4 in Section 9.3.3.6 Pulse Width Modulation Mode

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