ST7MC1/ST7MC2
INTERRUPTS (Cont’d)
Table 8. Interrupt Mapping
N°
Source
Block
Description
RESET Reset
TRAP
Software interrupt
0
MCES
Motor Control Emergency Stop
or Speed error interrupt
1
MCC/RTC Main clock controller time base interrupt
CSS
Safe oscillator activation interrupt
2
ei0
External interrupt port
3
ei1
External interrupt port
4
ei2
External interrupt port
5
Event U or Current Loop or Sampling Out
6
MTC
Event R or Event Z
7
Event C or Event D
8
SPI
SPI peripheral interrupts
9
TIMER A TIMER A peripheral interrupts
10
TIMER B TIMER B peripheral interrupts
11
LINSCI LINSCI Peripheral interrupts
12
AVD/
ADC
Auxiliary Voltage detector interrupt
ADC End of conversion interrupt
13
PWM ART PWM ART overflow interrupt
Register
Label
Priority
Order
Exit
from
HALT1)
Address
Vector
yes
N/A
no
MISR
MCRC
Highest
no
Priority
MCCSR
SICSR
yes
yes
N/A
yes
yes
no
MISR
no
no
SPICSR
yes
TASR
no
TBSR
no
Lowest
SCISR Priority no
SICSR
ADCSR
yes
ARTCSR
no
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
Note 1. Valid for HALT and ACTIVE-HALT modes except for the MCC/RTC or CSS interrupt source which exits from
ACTIVE-HALT mode only.
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