ST7PMC2N6B6(2004) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7PMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

5.3.3 Clock Security System (CSS)

The Clock Security System (CSS) protects the

ST7 against main clock problems. To allow the in-

tegration of the security features in the applica-

tions, it is based on a PLL which can provide a

backup clock. The PLL can be enabled or disabled

by option byte or by software. It requires an 8-MHz

input clock and provides a 16-MHz output clock.

5.3.3.1 Safe Oscillator Control

The safe oscillator of the CSS block is made of a

PLL.

If the clock signal disappears (due to a broken or

disconnected resonator...) the PLL continues to

provide a lower frequency, which allows the ST7 to

perform some rescue operations.

Automatically, the ST7 clock source switches back

from the safe oscillator if the original clock source

recovers.

5.3.3.2 Limitation detection

The automatic safe oscillator selection is notified

by hardware setting the CSSD bit of the SICSR

register. An interrupt can be generated if the CS-

SIE bit has been previously set.

These two bits are described in the SICSR register

description.

5.3.4 Low Power Modes

Mode

WAIT

HALT

Description

No effect on SI. CSS and AVD interrupts

cause the device to exit from Wait mode.

The CRSR register is frozen.

The CSS (including the safe oscillator) is

disabled until HALT mode is exited. The

previous CSS configuration resumes when

the MCU is woken up by an interrupt with

“exit from HALT mode” capability or from

the counter reset value when the MCU is

woken up by a RESET. The AVD remains

active, and an AVD interrupt can be used to

exit from Halt mode.

5.3.4.1 Interrupts

The CSS or AVD interrupt events generate an in-

terrupt if the corresponding Enable Control Bit

(CSSIE or AVDIE) is set and the interrupt mask in

the CC register is reset (RIM instruction).

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

CSS event detection

(safe oscillator acti- CSSD CSSIE Yes

vated as main clock)

AVD event

AVDF AVDIE Yes

Exit

from

Halt

No 1)

Yes

Note 1: This interrupt allows to exit from active-

halt mode.

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