ST7PMC2N6B6(2004) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7PMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

11.9 CONTROL PIN CHARACTERISTICS

11.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

VIH

Vhys

Input low level voltage 1)

Input high level voltage 1)

Schmitt trigger voltage hysteresis 2)

0.7xVDD

1

0.3xVDD

V

V

VOL Output low level voltage 3)

VDD=5V

IIO=+5mA

IIO=+2mA

0.5

1.2

V

0.2

0.5

IIO

Driving current on RESET pin

RON Weak pull-up equivalent resistor 1)

VIN=VSS, VDD=5V

2

20

40

mA

80

kΩ

tw(RSTL)out Generated reset pulse duration

Internal reset sources

30

µs

th(RSTL)in External reset pulse hold time 4)

2.5

µs

tg(RSTL)in Filtered glitch duration 5)

450

ns

Notes:

1. Data based on characterization results, not tested in production.

2. Hysteresis voltage between Schmitt trigger switching levels.

3. The IIO current sunk must always respect the absolute maximum rating specified in Section 11.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network protects the device against parasitic resets.

Figure 140. Typical Application with RESET pin 1)2)3)4)5)

Recommended

if LVD is disabled

VDD

VDD

VDD

USER

EXTERNAL

RESET

CIRCUIT 8)

0.01µF 4.7kΩ

0.01µF

RON

Filter

Required if LVD is disabled

PULSE

GENERATOR

ST7FMC

INTERNAL

RESET

WATCHDOG

LVD RESET

Notes:

1. The reset network protects the device against parasitic resets.

2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

3. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below

the VIL max. level specified in Section 11.9.1 . Otherwise the reset will not be taken into account internally.

4. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure

that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-

ified for IINJ(RESET) in section 11.2.2 on page 244.

263/294

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