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ST7FMC2S5TC(2004) View Datasheet(PDF) - STMicroelectronics

Part Name
Description
MFG CO.
ST7FMC2S5TC Datasheet PDF : 294 Pages
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ST7MC1/ST7MC2
9.8 10-BIT A/D CONVERTER (ADC)
9.8.1 Introduction
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 10-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources. 4 of the
channels have dedicated circuitry and pins to re-
duce noise and leakage so as to improve the accu-
racy and reduce the sensitivity to analog source
impedance.
The result of the conversion is stored in 2 8-bit
Data Registers. The A/D converter is controlled
through a Control/Status Register.
9.8.2 Main Features
s 10-bit conversion
s Up to 16 channels with multiplexed input
s 2 software-selectable sample times
s External positive reference voltage VREF+ can
be independent from supply
Figure 125. ADC Block Diagram
s Linear successive approximation
s Data registers (DR) which contain the results
s Conversion complete status flag
s Maskable interrupt
s On/off bit (to reduce consumption)
The block diagram is shown in Figure 125.
9.8.3 Functional Description
9.8.3.1 Analog References
VREF+ and VREF- are the high and low level refer-
ence voltage pins. Conversion accuracy may
therefore be impacted by voltage drops and noise
on these lines. VREF+ can be supplied by an inter-
mediate supply between VDDA and VSSA to
change the conversion voltage range. VREF- must
be tied to VSSA. An internal resistor bridge is im-
plemented between VREF+ and VREF- pins, with a
typical value of 15k
9.8.3.2 Analog Power Supply
VDDA and VSSA are the supply and ground pins
providing power to the converter part. They must
fADC
PRESCALER
EOC PRSC1PRSC0 ADON CS3 CS2 CS1 CS0 ADCCSR
4
IT
request
AIN0
ADSTSADCIE
AIN1
MCCBCR
ANALOG
MUX
ANALOG TO DIGITAL
CONVERTER
AINx
ADCDRMSB D9 D8 D7 D6 D5 D4 D3 D2
ADCDRLSB 0 0 0 0 0 0 D1 D0
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