ST7PMC2N6B6(2004) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7PMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

CONTROL REGISTER B (MCRB)

Read/Write

Reset Value: 0000 0000 (00h)

7

6

5

4

3

2

1

0

0 CPB* HDM* SDM* OCV OS2* OS1 OS0

Bit 7= Reserved, must be kept at reset value.

Bit 6= CPB*: Compare Bit for Zero-crossing detec-

tion.

0: Zero crossing detection on falling edge

1: Zero crossing detection on rising edge

Bit 5= HDM*: Hardware Demagnetization event

Mask bit

0: Hardware Demagnetization disabled

1: Hardware Demagnetization enabled

Bit 4= SDM*: Simulated Demagnetization event

Mask bit

0: Simulated Demagnetization disabled

1: Simulated Demagnetization enabled

Bit 3 = OCV: Over Current Handling in Voltage

mode

0: Over Current protection is OFF

1:Over current protection is ON

This bit acts as follows

Table 61. Over current handling

CLIM bit CLI bit OCV bit Output effect Interrupt

0

0

x

Normal running

mode

No

0

1

x

PWM is put off as

Current loop effect

No

1

0

x

Normal running

mode

No

1

1

0

PWM is put off as

Current loop effect

Yes

All MCOx outputs

1

1

1

are put in reset Yes

state (MOE reset)

Bits 2:0 = OS2*, OS[1:0]: Operating output mode

Selection bits

Refer to the Step behaviour diagrams (Figure 107,

Figure 108) and Table 62, “Step Behaviour/ sen-

sorless mode,” on page 208.

These bits are used to define the various PWM

output configurations.

Note: OS2 is the only preload bit.

Table 62. Step Behaviour/ sensorless mode

OS2

bit

PWM after

C and

before D

OS1

bit

0

0

On High

Channels

1

0

1

On Low

Channels

1

PWM after

D and

before Z

On High

Channels

On Low

Channels

On High

Channels

On Low

Channels

OS0

0

1

0

1

0

1

0

1

PWM after

Z and

before next

C

On high

channels

On low

channels

On high

channels

On low

channels

On high

channels

On low

channels

On high

channels

On low

channels

Note: For more details, see Step behaviour dia-

grams (Figure 107 and Figure 108).

* Preload bits, new value taken into account at the

next C event. A C event is generated at each write

to MPHST in Direct Access mode.

208/294

1

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