ST7FMC2N6B6(2004) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

MFG CO.

ST7FMC2N6B6
(Rev.:2004)

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, BRUSHLESS MOTOR CONTROL, FIVE TIMERS, SPI, LINSCI™

STMicroelectronics 

ST7MC1/ST7MC2

MOTOR CONTROLLER (Cont’d)

9.6.9 Channel Manager

The channel manager consists of:

– A Phase State register with preload and polarity

function

– A multiplexer to direct the PWM to the low and/

or high channel group

– A tristate buffer asynchronously driven by an

emergency input

The block diagram is shown in Figure 106.

Figure 106. Channel Manager Block Diagram

PWM Generator

Sampling frequency

Current comparator

output

MCFR Register

CFF[2:0] bits

MCRA Register

DAC bit

C

MPHST Register

OO bits*

MPAR Register

OE[5:0] bits

MCRA Register

V0C1 bit

PWM generator

V

V

SQ

I

I

Filter

R

6

Phasen Register*

6

Channel [5:0]

Notes:

Reg Updated/Shifted on R

Regn Updated with Regn+1 on C

I Current Mode

V Voltage Mode

events:

C Commutation

Z BEFM Zero-crossing

DS,H End Of Demagnetization

E Emergency Stop

R+/- Ratio Updated (+1 or -1)

O Multiplier Overflow

1 Branch taken after C event

2 Branch taken after D event

MCRA Register

SR bit

3 MCRB Register

OS[2:0] bits*

Dead

Time

Dead

Time

Dead

Time

8

MDTG Register

MREF Register

6

HFE[1:0] bits

HFRQ[2:0] bits

5

Channel [5:0]

2

High frequency chopper

MPOL Register

x6

OCV bit 1

OP[5:0] bits

6

MCRA Register

CLIM bit

1

CLI bit 1

MOE bit

1

x6

* = Preload register, changes taken into account at next C event.

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