ST7FMC2N6B6(2004) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FMC2N6B6
(Rev.:2004)
(Rev.:2004)
STMicroelectronics
ST7FMC2N6B6 Datasheet PDF : 294 Pages
| |||
ST7MC1/ST7MC2
Pin n°
Pin Name
Level
Port
Input
Main
Outp function
ut (after
reset)
Alternate function 2)
71 55 56 37 -
72 56 1 38 -
73 57 2 39 -
74 58 3 40 -
75 59 - - -
76 60 - - -
-
PE0/
OCMP2_B
I/O CT HS X X
-
PE1/
OCMP1_B
I/O CT
XX
- PE2/ICAP2_B I/O CT
- PE3/ICAP1_B/ I/O CT
-
PE4/
EXTCLK_B
I/O CT
XX
XX
XX
- PE5
I/O CT
XX
77 61 4 41 1 29 VPP/ICCSEL I
78 62 5 42 2 30 MCO0 (HS) O
HS
79 63 6 43 3 31 MCO1 (HS) O
HS
80 64 7 44 4 32 MCO2 (HS) O
HS
X X Port E0 Timer B Output Compare 2
X X X Port E1 Timer B Output Compare 1
X X Port E2 Timer B Input Capture 2
X X X Port E3 Timer B Input Capture 1
X X Port E4
Timer B External Clock
source
X X X Port E5
Must be tied low. In the programming
mode when available, this pin acts as
the programming voltage input VPP./
ICC mode pin. See section 11.9.2 on
page 264
X MTC Output Channel 0
X MTC Output Channel 1
X MTC Output Channel 2
Notes:
1. In the interrupt input column, “eiX” defines the associated external interrupt vector. If the weak pull-up
column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. If two alternate function outputs are enabled at the same time on a given pin (for instance, MCPWMV
and MCDEM on PD1 on TQFP32), the two signals will be ORed on the output pin.
4. OSC1 and OSC2 pins connect a crystal/ceramic resonator or an external source to the on-chip oscilla-
tor; see Section 1 INTRODUCTION and Section 11.5 CLOCK AND TIMING CHARACTERISTICS for
more details.
5. MCCFI can be mapped on 2 different pins on 80 ,64 and 56-pin packages. This allows:
- either to use PC1 as a standard I/O and map MCCFI on AOZ with or without using the operational am-
plifier (selected case after reset),
- or to map MCCFI on PC1 and use the amplifier for another function.
The mapping can be selected in MREF register of motor control cell. See section MOTOR CONTROL for
more details.
6. MCZEM is mapped on PF1 on 80, 64 and 56-pin packages and on PD2 on 44 and 32-pins.
MCDEM is mapped on PF0 on 80, 64 and 56-pin packages and on PD1 on 44 and 32-pin packages.
7. MCPWMV is mapped on PC6 on 80 and 64-pin packages and on PD1 on 44,and 32-pins packages.
MCPWMW is mapped on PC7 on 80, 64 and 44-pin packages and on PD0 on 32-pins package.
8. On the chip, each I/O port has 8 pads. Pads that are not bonded to external pins are in input pull-up
configuration after reset. The configuration of these pads must be kept at reset state to avoid added cur-
rent consumption.
9. Once the MTC peripheral is ON (bits CKE=1 or DAC=1 in the register MCRA), the pin PC4 is configured
to an alternate function. PC4 is no longer usable as a digital I/O.
14/294
1
Share Link: 