PIC16C5X
FIGURE 7-13: WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
Watchdog
Timer
WDT Enable
EPROM Bit
0
M
1
U
X
PSA
PPoosststsccaalelerr
8 - to - 1 MUX
PS2:PS0
To TMR0
Note: T0CS, T0SE, PSA, PS2:PS0
are bits in the OPTION register.
0
1
MUX
WDT
Time-out
PSA
TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4
N/A
OPTION
—
— T0CS T0SE
Legend: Shaded boxes = Not used by Watchdog Timer,
– = unimplemented, read as '0', u = unchanged
Bit 3
PSA
Bit 2
PS2
Bit 1
PS1
Bit 0
PS0
Value on
Power-On
Reset
Value on
MCLR and
WDT Reset
--11 1111 --11 1111
DS30453B-page 40
Preliminary
© 1998 Microchip Technology Inc.