SST49LF008C-33-4C-NH View Datasheet(PDF) - Silicon Storage Technology
Part Name
Description
MFG CO.
SST49LF008C-33-4C-NH Datasheet PDF : 36 Pages
| |||
Advance Information
Ready/Busy
The Ready/Busy pin (RY/BY#), is an open drain output
which indicates the device is ready to accept data in an AAI
mode, or that the internal programming cycle is complete.
The pin is used in conjunction with the LD# pin to switch
between these two flag states (see Table 19).
Load Enable
The Load Enable pin (LD#), is an input pin which when low,
indicates the host is loading data in an AAI programming
cycle. Data is loaded in the SST49LF00xC at the rising
edge of the clock. If LD# is high, it signals the AAI interface
that the host is terminating the command. LD# low/high
switches the RY/BY# output from buffer free flag to pro-
gramming complete flag (see Table 19).
No Connection (NC)
These pins are not connected internally.
DESIGN CONSIDERATIONS
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
VSS less than 1 cm away from the VDD pin of the device.
Additionally, a low frequency 4.7 µF electrolytic capacitor
from VDD to VSS should be placed within 1 cm of the VDD
pin. If you use a socket for programming purposes add an
additional 1-10 µF next to each socket. The RST# pin must
remain stable at VIH for the entire duration of an Erase
operation. WP#/AAI must remain stable at VIH for the entire
duration of the Erase and Program operations for non-Boot
Block sectors. To write data to the top Boot Block sectors,
the TBL# pin must also remain stable at VIH for the entire
duration of the Erase and Program operations.
MODE SELECTION
The SST49LF00xC flash memory device operates in two
distinct interface modes: the LPC mode and the Auto
Address Increment (AAI) mode. The WP#/AAI pin is used
to set the interface mode selection. The device is in AAI
mode when the WP#/AAI pin is set to the Supervoltage VH
(9±0.5V), and in the LPC mode when the WP#/AAI is set to
VIL/VIH. The mode selection must be configured prior to
device operation.
4 Mbit / 8 Mbit LPC Serial Flash
SST49LF004C / SST49LF008C
LPC MODE
Device Operation
The SST49LF00xC supports Multi-Byte Firmware Memory
Read and Write cycle types as defined in Intel Low Pin
Count Interface Specification, Revision 1.1. Table 2 shows
the size of transfer supported by the SST49LF00xC.
TABLE 2: TRANSFER SIZE SUPPORTED
Cycle Type
Firmware Memory Read
Firmware Memory Write
Size of Transfer
1, 2, 4, 16, 128 Bytes
1, 2, 4 Bytes
T2.0 1292
The LPC mode uses a 5-signal communication interface:
one control line, LFRAME#, which is driven by the host to
start or abort a bus cycle, a 4-bit data bus, LAD[3:0], used
to communicate cycle type, cycle direction, ID selection,
address, data and sync fields. The device enters standby
mode when LFRAME# is taken high and no internal opera-
tion is in progress.
The host drives LFRAME# signal from low-to-high to cap-
ture the start field of a LPC cycle. On the cycle in which
LFRAME# goes inactive, the last latched value is taken as
the START value. The START value determines whether
the SST49LF00xC will respond to a Firmware Memory
Read/Write cycle type as defined in Table 3.
TABLE 3: FIRMWARE MEMORY CYCLES START
FIELD DEFINITION
START
Value Definition
1101 Start of a Firmware Memory Read cycle
1110 Start of a Firmware Memory Write cycle
T3.0 1292
See following sections on details of Firmware Memory
cycle types (Tables 4 and 5). Two-cycle Program and
Erase command sequences are used to initiate Firmware
Memory Program and Erase operations. See Table 8 for a
listing of Program and Erase commands.
©200 Silicon Storage Technology, Inc.
12
S71292-00-000
1/06
Share Link: 