Data Sheet
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF202 / SST32HF402 / SST32HF802
ADDRESSES AMSS-0
WE#
TWCS
TWPS
TWRS
BES#
TBWS
TASTS
TAWS
TBYWS
UBS#, LBS#
TDSS TDHS
DQ15-8, DQ7-0
NOTE 2
VALID DATA IN
NOTE 2
1209 F04.0
FIGURE
Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance.
2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied.
5: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1
ADDRESSES AMSF-0
TRC
BEF#
TBE
OE#
VIH
WE#
TOE
TOLZ
DQ15-0
HIGH-Z
TBLZ
AMSF = Most Significant Flash Address
TAA
TOH
DATA VALID
TOHZ
TBHZ
DATA VALID
HIGH-Z
1209 F05.0
FIGURE 6: FLASH READ CYCLE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
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S71209-06-000
5/05