SI5328C-C-GMR View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

SI5328C-C-GMR

ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5328

Register 132.

Bit

D7

Name

Type

D6

D5

Reserved

R

D4

D3

D2

D1

D0

FOS2_FLG FOS1_FLG LOL_FLG Reserved

R/W

R/W

R/W

R

Reset value = 0000 0010

Bit

Name

Function

7:4 Reserved Reserved.

3 FOS2_FLG CLKIN_2 Frequency Offset Flag.

0: Normal operation.

1: Held version of FOS2_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by FOS2_MSK bit. Flag cleared by writing 0 to

this bit.

2 FOS1_FLG CLKIN_1 Frequency Offset Flag.

0: Normal operation

1: Held version of FOS1_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by FOS1_MSK bit. Flag cleared by writing 0 to

this bit.

1

LOL_FLG PLL Loss of Lock Flag.

0: PLL locked

1: Held version of LOL_INT. Generates active output interrupt if output interrupt pin is

enabled (INT_PIN = 1) and if not masked by LOL_MSK bit. Flag cleared by writing 0 to

this bit.

0

Reserved Reserved.

52

Rev. 1.0

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