SI5328C-C-GM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

SI5328C-C-GM

ITU-T G.8262 SYNCHRONOUS ETHERNET JITTER-ATTENUATING CLOCK MULTIPLIER

Silicon Laboratories 

Si5328

Register 3.

Bit

D7

D6

D5

D4

D3

D2

D1

D0

Name CKSEL_REG [1:0]

DHOLD SQ_ICAL

Reserved

Type

R/W

R/W

R/W

R

Reset value = 0000 0101

Bit

Name

Function

7:6 CKSEL_REG [1:0] CKSEL_REG.

If the device is operating in register-based manual clock selection mode

(AUTOSEL_REG = 00), and CKSEL_PIN = 0, then these bits select which input

clock will be the active input clock. If CKSEL_PIN = 1 and AUTOSEL_REG = 00,

the CS_CA input pin continues to control clock selection and CKSEL_REG is of no

consequence.

00: CKIN_1 selected.

01: CKIN_2 selected.

10: Reserved

11: Reserved

5

DHOLD

DHOLD.

Forces the part into digital hold. This bit overrides all other manual and automatic

clock selection controls.

0: Normal operation.

1: Force digital hold mode. Overrides all other settings and ignores the quality of

all of the input clocks.

4

SQ_ICAL

SQ_ICAL.

This bit determines if the output clocks will remain enabled or be squelched (dis-

abled) during an internal calibration. See Table 9 on page 20.

0: Output clocks enabled during ICAL.

1: Output clocks disabled during ICAL.

3:0

Reserved

Reserved.

Rev. 1.0

25

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