CS8405A-CS(2002) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8405A-CS Datasheet PDF : 36 Pages
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CS8405A
8.11 Interrupt 2 Mode MSB (Dh) and Interrupt Mode 2 LSB(Eh)
7
6
5
4
3
2
1
0
0
0
0
0
0
EFTU1
0
0
0
0
0
0
0
EFTU0
0
0
The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to
set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be-
comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active
on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in-
terrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These reg-
isters default to 00.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
8.12 Channel Status Data Buffer Control (12h)
7
6
5
4
3
2
1
0
0
0
BSEL
0
0
EFTCI
CAM
0
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
Default = ‘0’
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
Note:
There are separate complete buffers for the Channel Status and User bits. This control bit determines which
buffer appears in the address space.
EFTCI - E to F C-data buffer transfer inhibit bit.
Default = ‘0’
0 - Allow C-data E to F buffer transfers
1 - Inhibit C-data E to F buffer transfers
CAM - C-data buffer control port access mode bit
Default = ‘0’
0 - One byte mode
1 - Two byte mode
22
DS469PP4
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