CS8427-IS View Datasheet(PDF) - Cirrus Logic
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MFG CO.
CS8427-IS Datasheet PDF : 59 Pages
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CS8427
19. APPENDIX C: PLL FILTER
19.1 General
An on-chip Phase Locked Loop (PLL) is used to re-
cover the clock from the incoming data stream.
Figure 30 is a simplified diagram of the PLL in
these parts. When the PLL is locked to an AES3 in-
put stream, it is updated at each preamble in the
AES3 stream. This occurs at twice the sampling
frequency, FS. When the PLL is locked to ILRCK,
it is updated at FS so that the duty cycle of the input
doesn’t affect jitter.
There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is
important. For this reason, the PLL has been de-
signed to have good jitter attenuation characteris-
tics, as shown in Figure 33, Figure 34, Figure 35,
and Figure 36. In addition, the PLL has been de-
signed to only use the preambles of the AES3
stream to provide lock update information to the
PLL. This results in the PLL being immune to data
dependent jitter affects because the AES3 pream-
bles do not vary with the data.
The PLL has the ability to lock onto a wide range of
input sample rates with no external component
changes. If the sample rate of the input subse-
quently changes, for example in a varispeed appli-
cation, the PLL will only track up to ±12.5% from
the nominal center sample rate. The nominal cen-
ter sample rate is the sample rate that the PLL first
locks onto upon application of an AES3 data
stream or after enabling the CS8415A clocks by
setting the RUN control bit. If the 12.5% sample
rate limit is exceeded, the PLL will return to its wide
lock range mode and re-acquire a new nominal
center sample rate.
INPUT
Phase
Comparator
and Charge Pump
VCO
Rfilt
Crip
Cfilt
RMCK
÷N
Figure 30. PLL Block Diagram
54
DS477F1
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