CS8415A-IS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS8415A-IS

96 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8415A

9. PIN DESCRIPTION - SOFTWARE MODE

SDA/CDOUT 1

AD0/CS 2

EMPH 3*+

RXP0 4*

RXN0 5*

VA+ 6*

AGND 7*

FILT 8*

RST 9*

RMCK 10*

RERR 11*

RXP1 12

RXP2 13

RXP3 14

28 SCL/CCLK

27 AD1/CDIN

26 RXP6

25 RXP5

*24 H/S

*23 VL+

*22 DGND

*21 OMCK

20 U

19 INT

*18 SDOUT

*17 OLRCK

*16 OSCLK

15 RXP4

* Pins which remain the same function in all modes.

+ Pins which require a pull up or pull down resistor

to select the desired startup option.

SDA/CDOUT 1 Serial Control Data I/O (I2C) / Data Out (SPI) (Input/Output) - In I2C mode, SDA is the control I/O data

line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode, CDOUT is the out-

put data from the control port interface on the CS8415A

AD0/CS

2 Address Bit 0 (I2C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the

CS8415A into SPI control port mode. With no falling edge, the CS8415A defaults to I2C mode. In I2C

mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the

CS8415A

EMPH

3 Pre-Emphasis (Output) - EMPH is low when the incoming Channel Status data indicates 50/15 µs pre-

emphasis. EMPH is high when the Channel Status data indicates no pre-emphasis or indicates pre-

emphasis other than 50/15 µs. This is also a start-up option pin, and requires a 47 kΩ resistor to either

VL+ or DGND, which determines the AD2 address bit for the control port in I2C mode

RXP0

RXN0

4 AES3/SPDIF Receiver Port (Input) - Differential line receiver inputs carrying AES3 data. RXP0 may be

5 used as a single-ended input as part of 7:1 S/PDIF Input MUX. If RXP0 is used in MUX, RXN0 must be

ac coupled to ground.

RXP1

RXP2

RXP3

RXP4

RXP5

RXP6

12 Additional AES3/SPDIF Receiver Port (Input) - Single-ended receiver inputs carrying AES3 or S/PDIF

13 digital data. These inputs, along with RXP0, comprise the 7:1 S/PDIF Input Multiplexer and select line

14 control is accessed using the MUX2:0 bits in the Control 2 register. Please note that any unused inputs

15 should be tied to ground. See Appendix A for recommended input circuits.

25

26

VA+

6 Positive Analog Power (Input) - Positive supply for the analog section. Nominally +5 V. This supply

should be as quiet as possible since noise on this pin will directly affect the jitter performance of the

recovered clock

AGND

7 Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-

nected to a common ground area under the chip.

FILT

8 PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. See

“Appendix C: PLL Filter” on page 40 for recommended schematic and component values.

RST

9 Reset (Input) - When RST is low, the CS8415A enters a low power mode and all internal states are

reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are

stable in frequency and phase. This is particularly true in hardware mode with multiple CS8415A devices

where synchronization between devices is important

28

Share Link: