SC4524CSETRT View Datasheet(PDF) - Semtech Corporation

Part Name

Description

MFG CO.

SC4524CSETRT

28V 2A Step-Down Switching Regulator

Semtech Corporation 

SC4524C

Applications Information (Cont.)

Loop Compensation

The goal of compensation is to shape the frequency

response of the converter so as to achieve high DC

accuracy and fast transient response while maintaining

loop stability (see Figure 7).

It has an ESR zero FZ at

ωZ

=



R ESRCO

CONTROLLER AND SCHOTTKY DIODE

Io

CA

Rs

REF

+

EA

FB

-

Vc

Vramp

PWM

MODULATOR

COMP

C5

C8

R7

SW

L1

Co

Resr

Vo

R4

R6

It has a dominant low-frequency pole FP at

ωp

≈



RCO

and double poles at half the switching frequency.

Including the voltage divider (R4 and R6), the control to

feedback transfer function is found and plotted in Figure

8 as the converter gain.

Figure 7. Block diagram of control loops

The block diagram in Figure 7 shows the control loops of a

buck converter with the SC4524C. The inner loop (current

loop) consists of a current sensing resistor (Rs=5.5mW) and

a current amplifier (CA) with gain (GCA=18.5). The outer

loop (voltage loop) consists of an error amplifier (EA), a

PWM modulator, and a LC filter.

Since the current loop is internally closed, the remaining

task for the loop compensation is to design the voltage

compensator (C5, R7, and C8).

Since the converter gain has only one dominant pole at

low frequency, a simple Type-2 compensation network

is sufficient for voltage loop compensation. As shown in

Figure 8, the voltage compensator has a low frequency

integrator pole, a zero at FZ1, and a high frequency pole

at FP1. The integrator is used to boost the gain at low

frequency. The zero is introduced to compensate the

excessive phase lag at the loop gain crossover due to the

integrator pole (-90deg) and the dominant pole (-90deg).

The high frequency pole nulls the ESR zero and attenuates

high frequency noise.

60

For a converter with switching frequency FSW, output

inductance L1, output capacitance CO and loading R, the

control (VC) to output (VO) transfer function in Figure 7 is

given by:

Vo =

GPWM( + sRESR CO )

Vc ( + s / ωp )( + s / ωn Q + s2 / ωn2 )

This transfer function has a finite DC gain

30

0

-30

-60

1K

Fz1

Fp1

Fp

COMPENSATOR GAIN

CONVERTER

Fc

GAIN

LOOP GAIN

Fz Fsw/2

10K

100K

1M

10M

FREQUENCY (Hz)

GPWM

≈

R

GCA x

RS

Figure 8 — Bode plots for voltage loop design

14

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