SC4612HSTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC4612HSTRT Datasheet PDF : 18 Pages
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SC4612H
Applications Information (continued)
Over Current Protection
The SC4612H features low side MOSFET RDS(ON)
current sensing and hiccup mode over current
protection. The voltage across the bottom FET is
sampled approximately 150ns after it is turned on
to prevent false tripping due to ringing of the phase
node.
The internally set over current threshold is 100mV
typical. This can be adjusted up or down by
connecting a resistor between ILIM and DRV or GND
respectively. When programming with an external
resistor, threshold set point accuracy will be degraded
to 30%. The FET RDS(ON) at temperature will typically
be 150% or more of the room temperature value.
Allowance should be made for these sources of error
when programming a threshold value. When an
over current event occurs, the SC4612H immediately
disables both gate drives. The SS ramp continues to
its final value, if not already there. Once at final value,
the SS capacitor is discharged at approximately 1uA
until SS low value is reached (approx 0.8V). The SS/
Hiccup cycle will then repeat until the fault condition
is removed and the SC4612H starts up normally on
the next SS cycle.
Gate Drive/Control
The SC4612H provides integrated high current
drivers for fast switching of large MOSFETs. The
higher gate current will reduce switching losses of
the larger MOSFETs.
The low side gate drive is supplied directly from
the DRV. The high side gate drive is bootstraped
from the DRV pin. Cross conduction prevention
circuitry ensures a non overlapping (30ns typical)
gate drive between the top and bottom MOSFETs.
This prevents shoot through losses which provides
higher efficiency. Typical total minimum off time for
the SC4612H is about 30ns.
Error Amplifer Design
The SC4612H is a voltage mode buck controller that
utilizes an externally compensated high bandwidth
error amplifier to regulate the output voltage. The
power stage of the synchronous rectified buck
converter control-to-output transfer function is as
shown below.
GVD (s)
=
VIN
VR
1+
1+ s
sCRESR
L + s2LC
RL
where,
VIN = Input voltage
L = Output inductance
RESR = Output capacitor ESR
VR = Peak to peak ramp voltage
RL = Load resistance
C = Output capacitance
. . . . . . . . . (2)
The classical Type III compensation network can be
built around the error amplifier as shown below:
Fig 1. Type III compensation network
The transfer function of the compensation network
is as follows:
GCOMP
(s)
=
ω1
s
⋅
1+
1+
s
ωZ1
s
ωP1
1+
1+
s
ωZ2
s
ωP2
. . . . . . . . . (3)
where,
( ) ωZ1
=
1
R2C1
,
ωZ2 =
1
R1 + R3
C2
( ) ω1
=
R1
1
C1 +
C3
,
ωP1
=
1
R3C2
ωP2
=
1
R
2
C1C3
C1 + C
3
The design guidelines are as following:
1. Set the loop gain crossover frequency wC for given
switching frequency.
2. Place an integrator at the origin to increase DC
and low frequency gains.
3. Select wZ1 and wZ2 such that they are placed near
wO to dampen peaking; the loop gain should cross
10
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