SC4210AEVB View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC4210AEVB Datasheet PDF : 11 Pages
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SC4210A
POWER MANAGEMENT
Applications Information (Cont.)
Using the above values with a constant 3A load gives
80º PM (phase margin) with a unity gain frequency of
2.4MHz; see Figure 3, simulated in P-Spice.
ZL
:
=
s
1
CL
+
Re sr
Gs
:
=
RL
RL
•
+
ZL
ZL
Gs
:
=
RL
s
1
CL
+
Re sr
RL
+
s
1
CL
+
Re
sr
Hs
:
=
R5
(R4 + R5)
•
FS
•
GS
Figure 3.
Compensating the SC4210A can be done by modeling
the device in a straight forward fashion using the Control
Loop Block Diagram shown in Figure 1.
ZC
:
=
RC s
+
1
RC •CC
s
RO
:
=
0.26
• 107
0.26
βnpn • R3
• 107 + βnpn
• R3
The basic analysis yields a two pole, two zero system.
However, considering a limited bandwidth of the NPN
buffer stage and external N-MOSFET, the system
eventually rolls off due to the third pole at very high
frequencies (10-20MHz). The low ESR ceramic capacitors
push the secondary zero to well above the unity gain
frequency, requiring accurate placement of the dominant
zero for stability.
To adjust the above values, say for an output capacitor
of 1µF ceramic (ESR=1mΩ), the Rcomp initially should
be decreased by the same multiple as the output
capacitor, i.e. Rcomp = 24kΩ ÷ 10 = 2.4kΩ. Simulated
results yield over 90º of PM at a unity gain frequency of
386kHz; see Figure 4.
FS
:
=
gm • Ro • Zc
Ro + Zc
gm
:
=
0.8
mA
V
Fs
:
=
(0.26
• 107
)•
0.3
• 107βnpn
•
R3
•
s
Cc
+
0.26
(s Rc •
• 107 • s
Cc
Rc
+ 1)R3 • βnpn • gm
• Cc + βnpn • R3 • s
Rc
•
Cc
+
0.26
• 107
+
βnpn
• R3
FB
:
=
R5
R4 + R5
2004 Semtech Corp.
7
www.semtech.com
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