SC403BEVB View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC403BEVB Datasheet PDF : 32 Pages
| |||
SC403B
Applications Information (continued)
PCB Layout Guidelines
The optimum layout for the SC403B is shown in Figure 15.
This layout shows an integrated FET buck regulator with a
maximum current of 6A. The total PCB area is approxi-
mately 25 x 29 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
• IC decoupling capacitors
• PGND plane
• AGND island
• FB, VOUT, and other analog control signals
• BST, ILIM, and LX
• CIN and COUT placement and current loops
IC Decoupling Capacitors
• A 0.1 μF capacitor must be located as close as
possible to the IC and directly connected to pins
3 (VDD) and 4 (AGND).
• All other decoupling capacitors must be located
as close as possible to the IC.
PGND Plane
• PGND requires its own copper plane with no
other signal traces routed on it.
• Copper planes, multiple vias and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the
device.
• The PGND copper area between the input
capacitors, output capacitors, and PGND pins
must be as tight and compact as possible to
reduce the area of the PCB that is exposed to
noise due to current flow on this node.
• Connect PGND to AGND with a short trace or
0Ω resistor. This connection should be as close
to the device as possible.
All components
shown Top Side
VDD Decoupling Capacitor
Pin 1 marking
IC with vias for
LX, AGND, VIN
AGND plane on
inner layer
Vout sense trace
on inner layer
PGND on inner
or bottom layer
RFB2
LX plane on top and
RFB1
CTOP
L
bottom layer
CIN
CIN
COUT
Cer.
SP or
POSCAP
VOUT Plane on top
and bottom layer
RGND — AGND connects to VIN plane on
PGND close to IC
top and/or
bottom layer
PGND on top
layer
Figure 15 — PCB Layout
28
Share Link: 