SC2595STRT(2007) View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC2595STRT Datasheet PDF : 11 Pages
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POWER MANAGEMENT
Application Information (Cont.)
Layout guidelines
1)The SC2595 has a power SO-8 package. It can im-
prove the thermal impedance (θJC) significantly. A suitable
thermal pad should be added when PCB layout. Some
thermal vias are required to connect the thermal pad to
the PCB ground layer. This will improve the thermal per-
formance .
2)To increase the noise immunity, a ceramic capacitor of
10nf to 100nf is required to decouple the VREF pin with
the shortest connection trace, also A 10nF to 100nF
ceramic capacitor close to the VSENSE pin is required to
avoid oscillation during transient condition.
3)To reduce the noise on the input power rail for stan-
dard SSTL-2 application, a 68µF low ESR capacitor and
a 1µF ceramic capacitor have to be used on the input
power rail with shortest possible connection.
4)For lower power loss SSTL-2 application, a 220µF AL.
capacitor (ESR should be lower than 250m ohm) and a
10µF ceramic has to be added on the PVCC pin and a 1µF
ceramic capacitor +5.1 ohm filter has to be added on
the VDDQ pin with shortest possible connection.
5)VTT output copper plane should be as large as possible.
6)VSENSE trace should be as short as possible.
SC2595
© 2007 Semtech Corp.
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