SC2545TSTRT View Datasheet(PDF) - Semtech Corporation

Part Name

Description

MFG CO.

SC2545TSTRT

High Performance Wide Input Range Dual Synchronous Buck Controller

Semtech Corporation 

SC2545

POWER MANAGEMENT

Applications Information (Cont.)

Bottom Switch

The RMS current in bottom switch is given by

,4UPV

,R



'

G





The conduction losses are then

Pbc=IQ2,rms2 Rds(on).

where Rds(on) is the channel resistance of bottom MOSFET.

If the input voltage to output voltage ratio is high (e.g.

Vin=12V, Vo=1.5V), the duty ratio D will be small. Since

the bottom switch conducts with duty ratio (1-D), the

corresponding conduction losses can be quite high.

Due to non-overlapping conduction between the top and

the bottom MOSFET’s, the internal body diode or the

external Schottky diode across the drain and source

terminals always conducts prior to the turn on of the

bottom MOSFET. The bottom MOSFET switches on with

only a diode voltage between its drain and source

terminals. The switching loss is negligible due to near zero-

voltage switching.

The gate losses are estimated as

Main Control Loop Design

The goal of compensation is to shape the frequency re-

sponse charatericstics of the buck converter to achieve

a better DC accuracy and a faster transient response

for the output voltage, while maintaining the loop stabil-

ity.

The block diagram in Figure 10 represents the control

loop of a buck converter designed with the SC2545. The

control loop consists of a compensator, a PWM modula-

tor, and an LC filter.

The LC filter and PWM modulator represent the small

signal model of the buck converter operating at fixed

switching frequency. The transfer function of the model

is given by:

92

9&

9,1

9P

˜







V/

V5(65&

 5  V/&

5()



3:0

/

9R

5()

($ 02'8/$725



&R

=I

(55287

5HVU

5J

3 EJ

4 J 9 FF I V 

=V

5 JW

The total bottom switch losses are then

Pb=Pbc+Pbg.

Once the power losses for the top and bottom MOSFET’s

are known, thermal and package design at component

and system level should be done to verify that the

maximum die junction temperature (Tj,max, usually 125oC)

is not exceeded under the worst-case condition. The

equivalent thermal impedance from junction to ambient

(T ja) should satisfy

7 7

T d MPD[

 DPD[

T

ja

depends

on

MD

the

die

to

3sOuRVbV strate

bonding,

packaging

material, the thermal contact surface, thermal compound

property, the available effective heat sink area, and the

air flow condition (natual or forced convection). Actual

temperature measurement of the prototype should be

carried out to verify the thermal design.

Fig. 10. Block diagram of the control loop.

where VIN is the input voltage, Vm is the amplitude of the

internal ramp, and R is the equivalent load.

The model is a second order system with a finite DC gain,

a complex pole pair at Fo, and an ESR zero at Fz, as

shown in Figure 11. The locations of the poles and zero

are determined by:

)2



S /&2

)=



S 5H VU&2

ã 2005 Semtech Corp.

15

www.semtech.com

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