SC2544TSTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC2544TSTRT Datasheet PDF : 24 Pages
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SC2544
POWER MANAGEMENT
Applications Information (Cont.)
Bottom Switch
The RMS current in bottom switch is given by
IQ2,rms = Io
(1−
D)(1+
δ2
12
).
The conduction losses are then
Main Control Loop Design
The goal of compensation is to shape the frequency
response charatericstics of the buck converter to
achieve a better DC accuracy and a faster transient
response for the output voltage, while maintaining
the loop stability.
P
bc=
I
2
Q2,rms
Rds(on).
where Rds(on) is the channel resistance of bottom
MOSFET. If the input voltage to output voltage ratio
is high (e.g. Vin=12V, Vo=1.5V), the duty ratio D will
be small. Since the bottom switch conducts with duty
ratio (1-D), the corresponding conduction losses can
be quite high.
The block diagram in Figure 10 represents the control
loop of a buck converter designed with the SC2544. The
control loop consists of a compensator, a PWM modula-
tor, and an LC filter.
The LC filter and PWM modulator represent the small
signal model of the buck converter operating at fixed
switching frequency. The transfer function of the
model is given by:
Due to non-overlapping conduction between the top and
the bottom MOSFET’s, the internal body diode or the
external Schottky diode across the drain and source
VO
VC
=
VIN
Vm
⋅
1
+
1+
sL
sRESRC
/ R + s2LC
terminals always conducts prior to the turn on of the
bottom MOSFET. The bottom MOSFET switches on with
only a diode voltage between its drain and source
REF
+
PWM
L
Vo
terminals. The switching loss is negligible due to near zero-
REF
EA
MODULATOR
-
voltage switching.
Co
The gate losses are estimated as
P bg
=
Rg
R gt
Q g V cc f s .
The total bottom switch losses are then
ERROUT
Zf
Zs
Resr
Pb=Pbc+Pbg.
Fig. 10. Block diagram of the control loop.
Once the power losses for the top and bottom
MOSFET’s are known, thermal and package design
at component and system level should be done to
verify that the maximum die junction temperature
(T , j,max usually 125oC) is not exceeded under the
worst-case condition. The equivalent thermal
impedance from junction to ambient (θ ja) should
satisfy
θ ja
≤
Tj,max − Ta,max
Ploss
.
θ ja depends on the die to substrate bonding,
packaging material, the thermal contact surface,
thermal compound property, the available effective
heat sink area, and the air flow condition (natual or
forced convection). Actual temperature measurement
of the prototype should be carried out to verify the
thermal design.
where V is the input voltage, Vm is the amplitude of
IN
the internal ramp, and R is the equivalent load.
The model is a second order system with a finite DC
gain, a complex pole pair at Fo, and an ESR zero at
Fz, as shown in Figure 11. The locations of the poles
and zero are determined by:
FO = 2π
1
LCO
FZ
=
2π
1
Re srCO
2005 Semtech Corp.
15
www.semtech.com
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