SC2441AEVB(2006) View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC2441AEVB
(Rev.:2006)
(Rev.:2006)
Semtech Corporation
SC2441AEVB Datasheet PDF : 37 Pages
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SC2441A
POWER MANAGEMENT
Applications Information
In Figure 21,
Qgs1 is the gate charge needed to bring the gate-to-source
voltage Vgs to the threshold Vgs_th,
Qgs2 is the additional gate charge required for the switch
current to reach
Qgd is the charge
its full-scale value
needed to charge
gIdas.taen-tdo-drain
(Miller)
capacitance when Vds is falling.
Switching losses occur during the time interval [t1, t3].
Defining tr = t3-t1. tr can be approximated as
tr
=
(Qgs2 + Qgd )Rgt .
Vcc - Vgsp
where R is the total resistance from the driver supply
gt
rail to the gate of the MOSFET. It includes the gate driver
internal impedance Rgi, external resistance Rge and the
gate resistance Rg within the MOSFET i.e.
Rgt = Rgi+Rge+Rg.
Vgsp is the Miller plateau voltage shown in Figure 21.
Similarly an approximate expression for tf is
IQ2,rms = Io
(1- D)(1+
d2
12
).
The conduction loss is then
Pbc=IQ2,rms2 Rds(on),
where Rds(on) is the channel resistance of bottom MOSFET.
If the input voltage to output voltage ratio is high (e.g.
Vin=12V, Vo=1.5V), the duty ratio D will be small. Since
the bottom switch conducts with duty ratio (1-D), the
corresponding conduction losses can be quite high.
Due to non-overlapping conduction between the top and
the bottom MOSFET’s, the internal body diode or the
external Schottky diode across the drain and source
terminals always conducts prior to the turn on of the
bottom MOSFET. The bottom MOSFET switches on with
only a diode voltage between its drain and source
terminals. The switching loss
Pbs
=
1
2
(
t
r
+ tf )(1+
d
2
)Io
Vdfs
is negligible due to near zero-voltage switching.
The gate loss is estimated as
tf
=
(Qgs2
+ Qgd )Rgt
Vgsp
.
Pbg
=
Rg
Rgt
QgVcc fs.
The total bottom switch loss is then
Only a portion of the total losses Pg = QgVccfs is dissipated
in the MOSFET package. Here Qg is the total gate charge
specified in the datasheet. The power dissipated within
the MOSFET package is
Ptg
=
Rg
Rgt
QgVcc fs.
The total power loss of the top switch is then
P = P +P +P .
t
tc ts tg
If the input supply of the power converter varies over a
wide range, then it will be necessary to weigh the relative
importance of conduction and switching losses. This is
because conduction loss is inversely proportional to the
input voltage. Switching loss however increases with the
input voltage. The total power loss of MOSFET should be
calculated and compared for high-line and low-line cases.
The worst case is then used for thermal design.
Pb=Pbc+Pbs+Pbg.
Once the power losses Ploss for the top (Pt) and bottom
(Pb) MOSFET’s are known, thermal and package design
at component and system level should be done to verify
that the maximum die junction temperature (Tj,max, usually
125oC) is not exceeded under the worst-case conditions.
The equivalent thermal impedance from junction to
ambient (θja) should satisfy
q ja
£
Tj,max - Ta,max
Ploss
.
θja depends on the die to substrate bonding, packaging
material, the thermal contact surface, thermal compound
property, the available effective heat sink area and the
air flow condition (free or forced convection). Actual
temperature measurement of the prototype should be
carried out to verify the thermal design.
Bottom Switch:
The RMS current in bottom switch can be calculated
2006 Semtech Corp.
Integrated Power MOSFET Drivers
There are four internal MOSFET drivers in a dual-
channel step-down converter.
31
www.semtech.com
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