SC1544TS-3.3TR View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC1544TS-3.3TR Datasheet PDF : 15 Pages
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SC1544
POWER MANAGEMENT
Applications Information
Theory Of Operation
The SC1544 provides a simple way to power five seperate
voltage buses while controlling them correctly using the
ACPI control interface (PWR_OK, /SLP_S3 and /SLP_S5).
PRELIMINARY
To prevent false latching due to capacitor inrush currents,
low supply rails or momentary overloads, the current limit
latch has a timer. If VOUT is above the OCP threshold (VTH(OC))
before the timer times out, then the outputs do not
latch.
It requires only a single supply rail (5VSB from the system
silver box) to operate. An internal charge pump generates
the gate voltages required to enable the use of n-channel
.ETs throughout the design. The external .ETs are
operated in two discrete modes:
1) as pass devices where VOUT = VIN - (IOUT * RDS(ON))
2) as linear regulators.
Please refer to the Gates At A Glance section on page
8 and the Typical Applications Circuits on page 11 to
determine which .ETs operate in which mode.
Linear Mode: the SC1544 contains a bandgap reference
trimmed for optimal temperature coefficient which is fed
into the inverting input of an error amplifier. The output
voltage of each linear regulator (monitored by the sense
pin for that output) is divided down internally using a
resistor divider and compared to the bandgap voltage.
The error amplifier drives the gate of the appropriate
external .ET to maintain the voltage at the non inverting
input, and hence the output voltage.
Reducing Commutation Noise
The slew rate of the linears is slow enough to provide
soft commutation. The non-linear switch outputs (5V and
3.3V Duals) have fast slew rates. It may be necessary to
put a resistor in series with the gate to reduce transients
(3.3V Dual Memory shown):
3.3V
Q5
IRLR3103
R1
10k (typ.)
3.3V DUAL MEM
U1
1
G5
2
3.3VDM
3
G6
4
G7
5
AGP
6
TYPEDET
7
PWR_OK
8
EN
9
/S3
10
/S5
11
USB
12
PCI
SC1544-3.3
24
G8
23
1.8V
22
G4
21
3.3VD
20
GND
19
G2/3
18
G1
17
5VD
16
5VSB
15
FC
14
+CAP
13
-CAP
Pass Device Mode: when a particular output is enabled
(please refer to the Power Matrix section on page 8) in
pass mode (i.e. 5VSB to 5V Dual), the appropriate gate
drive will be driven high to turn the .ET hard on, minimizing
the voltage drop due to IOUT*RDS(ON).
The sense pins serve two functions:
1) to sense the output voltage for the linear regulators
2) to sense the output voltage for over current protection
Over Current Protection is provided for all dual outputs.
OCP is implemented by utilizing the RDS(ON) of the .ETs. As
the output current increases, the regulation loop
maintains the output voltage (linear mode only) by turning
on the .ET more and more. Eventually, as the RDS(ON) low
limit is reached (pass devices are already operating at
this point) the .ET will be unable to turn on any further
and the output voltage will start to fall. When the output
voltage falls to approximately 50% of nominal, all outputs
are latched off. Toggling the enable pin or cycling 5VSB
will reset the latch.
Another possible source of commutation noise occurs at
startup on 3.3V Dual Memory, when the standby .ET, Q6
and the pass-through .ET, Q5 are both off. 3.3V Dual
Memory will charge to 3.3V minus 0.7V (the drop across
the Q5 body diode). When PWR_OK asserts, Q6 turns on
shorting 3.3V to 3.3V Dual Memory, pulling it down locally
momentarily. This should not be an issue as long as there
is sufficient capacitance on 3.3V locally. Another way to
reduce this drop is to place a schottky diode across Q5
with the cathode towards 3.3V Dual Memory so this rail
charges to 3.3V minus 0.4V, thus reducing the drop when
Q5 turns on:
3.3V
C1 +
Increase bulk capacitance (preferred)
Q5
IRLR3103
3.3V DUAL MEM
TO PIN 1
D1 (optional)
TO PIN 2
2002 Semtech Corp.
12
www.semtech.com
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