PSD833G3V-C-12MI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD833G3V-C-12MI Datasheet PDF : 110 Pages
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PSD835G2
The
PSD835G2
Functional
Blocks
(cont.)
Figure 25. Peripheral I/O Mode
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PSD8XX Family
D0 - D7
DATA BUS
PF0 - PF7
9.4.3 Port Configuration Registers (PCRs)
Each port has a set of PCRs used for configuration. The contents of the registers can be
accessed by the microcontroller through normal read/write bus cycles at the addresses
given in Table 6. The addresses in Table 6 are the offsets in hex from the base of the
CSIOP register.
The pins of a port are individually configurable and each bit in the register controls its
respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,
shown in Table 22, are used for setting the port configurations. The default power-up state
for each register in Table 19 is 00h.
Table 19. Port Configuration Registers
Register Name
Port
MCU Access
Control
Direction
Drive Select*
E,F,G
A,B,C,D,E,F,G
A,B,C,D,E,F,G
Write/Read
Write/Read
Write/Read
*NOTE: See Table 26 for Drive Register bit definition.
57
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