PSD824G3V-C-70UI View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
PSD824G3V-C-70UI Datasheet PDF : 110 Pages
| |||
PSD835G2
The
PSD835G2
Functional
Blocks
(cont.)
PSD8XX Family
Table 17. Port Operating Mode Settings
Mode
Defined In
PSDsoft
Control
Register
Setting
MCU I/O
Declare
pins only
0
(Note 3)
Declare pins
PLD I/O
and logic
NA
equations
Data Port
(Port F)
Selected for
MCU with
NA
non-mux bus
Address Out
(Port E, F, G)
Declare
pins only
1
Declare pins or
Address In
logic equation
NA
(Port A,B,C,D,F) for input
Micro⇔Cells
Peripheral I/O Logic equations
NA
(Port F)
(PSEL0 & 1)
JTAG ISP
(Note 2)
Declare pins
only
NA
Direction
Register
Setting
1 = output,
0 = input
(Note 1)
(Note 1)
VM
Register
Setting
NA
NA
JTAG
Enable
NA
NA
NA
NA
NA
1 (Note 1)
NA
NA
NA
NA
NA
NA
PIO bit = 1
NA
NA
NA
JTAG_Enable
*NA = Not Applicable
NOTE: 1. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the
individual output enable product term (.oe) from the CPLD AND array.
2. Any of these three methods will enable JTAG pins on Port E.
3. Control Register setting is not applicable to Ports A, B and C.
9.4.2.1 MCU I/O Mode
In the MCU I/O Mode, the microcontroller uses the PSD835G2 ports to expand its own
I/O ports. By setting up the CSIOP space, the ports on the PSD4000 are mapped into the
microcontroller address space. The addresses of the ports are listed in Table 6.
A port pin can be put into MCU I/O mode by writing a ‘0’ to the corresponding bit in the
Control Register (Port E, F and G). The MCU I/O direction may be changed by writing to
the corresponding bit in the Direction Register, or by the output enable product term. See
the subsection on the Direction Register in the “Port Registers” section. When the pin is
configured as an output, the content of the Data Out Register drives the pin. When config-
ured as an input, the microcontroller can read the port input through the Data In buffer.
See Figure 22.
Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default.
They can be used for PLD I/O if they are specified in PSDsoft.
9.4.2.2 PLD I/O Mode
The PLD I/O Mode uses a port as an input to the CPLD’s Input Micro⇔Cells, and/or as an
output from the CPLD’s Output Micro⇔Cells. The output can be tri-stated with a control
signal. This output enable control signal can be defined by a product term from the PLD, or
by setting the corresponding bit in the Direction Register to ‘0’. The corresponding bit in the
Direction Register must not be set to ‘1’ if the pin is defined as a PLD input pin in PSDsoft.
The PLD I/O Mode is specified in PSDsoft by declaring the port pins, and then specifying
an equation in PSDsoft.
55
Share Link: 